Static and nonequilibrium transient conductance at strong carrier freeze-out in a buried channel, metal-oxide-semiconductor transistor

A simple model of the low temperature (T<30 °K), static and nonequilibrium transient conductance of the potential minimum region in a silicon, buried channel, metal-oxide-semiconductor field effect transistor is developed and experimental measurements of these conductances under carrier freeze-out conditions are presented. The transient, nonequilibrium conductance is considered as a potential mechanism for low voltage (∼25 mV), low switching energy (∼10 aJ), high density dynamic logic.