Layout-based statistical modeling for the prediction of the matching properties of MOS transistors

A new methodology for statistical mismatch analysis of MOS transistor pairs is presented. Size and shape, as well as placement and partitioning of devices are taken into account by using a statistical approach based on stochastic process theory. The method depends on device geometry and mutual distances between devices and has been developed by first defining a transformation which maps the statistical behavior of the technological parameters considered as sources of errors into the behavior of device parameters. A useful expression for the parameter mismatch variance depending on the layout has been derived by assuming a particular form for the autocorrelation function of process parameters. Finally, the method has been used to analyze and compare the mismatch effect on several interdigitated and common-centroid structures.