Temporal alignment of high-speed transmit channels of FPGA

A scalable alignment algorithm is described that corrects for random multiple-bit offsets among parallel transmit data streams of high-speed I/O-ports on an FPGA, as required for subsequent multiplexing or digital-to-analogue conversion. The temporal alignment of 17 parallel 10 Gbit/s transmit channels on a Xilinx Virtex II Pro X FPGA is demonstrated.