HERMeS: H igh-Fidelity and High-Speed E mulation with a R econfigurable Framework for DRAM-Based Processing-in- M emory S ystems

Rapid advancements in large-scale deep neural networks (DNNs) have increased the demand for substantial data storage and memory bandwidth, resulting in the well-known data movement bottleneck in traditional von Neumann-based architectures. Processing-in-memory (PIM) technology, which integrates computation within memory, has emerged as a promising solution to address this challenge. Previous PIM research utilized in-house PIM simulators to validate this new architecture; however, evaluation performed using in-house PIM simulators suffers from lower versatility and slower evaluation runtimes than emulation. To address these limitations, we present HERMeS , a high-speed, trace-based PIM emulation platform that offers high reliability, fidelity, and versatility. HERMeS separates the PIM controller and PIM emulator regions to achieve a modular design, enhancing versatility, and leverages SystemVerilog to enable high-fidelity implementation on field-programmable gate arrays (FPGAs). To maximize the speedup, we introduce a minimal block RAM (BRAM) unit ( i.e. , pim-tile ) to efficiently manage the limited BRAM resources of the FPGA and optimization techniques to prevent runtime degradation caused by the underutilized pim-tile . We demonstrate the versatility of HERMeS within the class of DRAM-based bank- and bank-group-level digital PIM architectures by implementing representative pre-existing designs in this domain, including AiM and PIM-HBM. Because these target architectures are designed to accelerate DNN inference, the evaluation is conducted primarily on DNN inference workloads, which constitute the natural application domain of this class of PIM designs. Compared to existing in-house PIM simulators, HERMeS demonstrates exceptional accuracy with an average cycle error rate of just 1.57%, while achieving up to 230.24 \(×\) faster runtime, underscoring its efficacy as a high-performance PIM emulation framework.