A device model which describes the behavior of thin-film transistors fabricated in crystalline silicon on glass is introduced. The dc current–voltage characteristics of fully depleted thin-film silicon p-channel enhancement-mode MOSFETs operated in accumulation is provided. Physically derived expressions are presented for drain current in the accumulation and depletion regions which include the correct dependence on drain voltage, film thickness, and doping level. A C-∞model is realized from cutoff to accumulation by using an interpolant around the flatband voltage and a hyperbolic tangent blending function. The device model shows excellent agreement with measured results for output, transfer, and transconductance characteristics. A compact circuit simulation model has also been implemented in the Spectre circuit simulator using Verilog-A.
No takes yet. Share an insight, caveat, or question.
Nassar et al. (2009) studied this question.
Synapse has enriched 2 closely related papers on similar clinical questions. Consider them for comparative context: