As technology scales to 32 nm and functional frequency and density continue to rise, PSN effects, which can reduce a circuit's noise immunity and could lead to failures, pose new challenges to chip manufacturers and foundries. This article provides an overview of low-power and delay testing, and surveys ongoing research for analyzing and dealing with PSN effects during delay test and timing analysis.
No takes yet. Share an insight, caveat, or question.
Tehranipoor et al. (2010) studied this question.
Synapse has enriched one closely related paper. Consider it for comparative context: