Low cost architecture of direct conversion digital receiver

The paper presents a low-cost architecture for a direct conversion digital receiver that uses six-port technology. An experimental prototype has been constructed and tested. Analogue carrier recovery and decision circuits are investigated as a means to provide future system integration and high data rate capacity. The designed receiver is operated at an ISM frequency of 2.45 GHz and uses a QPSK modulation format. Results on data rate limitations are given for QPSK signals up to 52 Mb/s. Test results related to adjacent channel, co-channel and CW interferences are presented for a data rate of 40 Mb/s. Phase offset between carrier and reference signals, along with carrier frequency deviation performances, are also presented for a rate of 40 Mb/s. A frequency hopping spread spectrum technique is discussed on the basis of the proposed architecture.