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In this paper, a RESURF high voltage (HV) nLDMOS is designed in 0.35 μm BiCMOS technology (STMicroelectronics technology-like). Optimization of the key device/process parameters of the device is performed using analytical approach and verified using advanced 2D numerical simulation. The results show excellent RON,SP/BV trade-off (BV ≈ 400 V and RON,SP = 9.5 mΩ cm2 for Tepi = 4 μm and LDrift = 17 μm) without any added process complexity. The maximum obtained drain current is 1.8 mA/μm at a gate voltage of 5 V. The designed device is suitable for smart power integration.
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Abouelatta et al. (2015) studied this question.
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