Understanding LER-Induced MOSFET VT Variability—Part I: Three-Dimensional Simulation of Large Statistical Samples

In this paper, using computationally intensive 3-D simulations in a grid computing environment, we perform a detailed study of line-edge-roughness (LER)-induced threshold voltage variability in contemporary MOSFETs. Statistical ensembles of tens of thousands transistors have been simulated. Our analysis has been predominantly performed on a 35-nm channel-length bulk MOSFET test bed, widely used in previous studies to investigate the impact of different statistical variability sources. Comprehensive data mining and statistical analysis provide information about the shape of the distribution of the device threshold voltage, which is significantly non-Gaussian. Strong nonlinear correlation has been observed between the threshold voltage and the average channel length of the simulated devices. The width dependence of LER-induced threshold voltage variability has also been simulated and analyzed. Additional confirmation of the basic conclusions from the simulation and statistical analysis of the 35-nm test bed transistor is provided by the simulation of a 42-nm physical channel-length bulk LP MOSFET, a 32-nm channel-length thin-body silicon-on-insulator (SOI) MOSFET, and a 22-nm channel-length double-gate (DG) MOSFET.