Drain-Engineered TFET With Fully Suppressed Ambipolarity for High-Frequency Application

In this paper, we propose and simulate a novel drain-engineered structure of a quadruple-gate tunnel fieldeffect transistor (TFET). The proposed device employs a lateral dual source with a vertical drain extension on top of T-shaped channel region. This enables the modification of screening length (λ) by varying the silicon film (tSi,v) and the oxide (tSi,v) thicknesses at the channel-drain junction to overcome the limitations of high ambipolar leakage in the conventional double-gate TFET (DG-TFET). A 2-D calibrated simulation study has revealed the doubling of on-current (ION) and significantly suppressed ambipolar leakage (IAMB) in the proposed device as compared to the conventional DG-TFET. Furthermore, a five orders of magnitude improvement in ION/IOFF, 73% increase in transconductance (gm), 62% increase in cutoff frequency (fT), 72% increase in gain-bandwidth product, and 54% improvement in fall propagation delay (tpHL) are achieved in the proposed device.