Paralleled Operation of High-Voltage Cascode GaN HEMTs

Paralleling devices is an effective way to achieve a higher power application while still having the convenience of using discrete devices. However, the mechanisms of potential failures and the circuit design considerations have not been thoroughly studied yet, when paralleling gallium nitride high-electron-mobility transistors (GaN HEMTs) in cascode configuration. This paper presents a comprehensive study of paralleled high-voltage cascode GaN HEMTs, evaluating both circuit design and device characteristics. The mechanisms of current oscillation, which occurred during the cascode GaN HEMT parallel operation, are analyzed in detail. The Q3D tool and Spice-based simulation model jointly quantify the sensitivity of the circuit parasitic parameters and the cascode GaN HEMT mismatches during the paralleled operation. General design guidelines are provided in the paper as well. A group of experimental results ultimately validate the analysis toward parallel operation.