Several key aspects of HgCdTe metal–insulator–semiconductor (MIS) device physics affecting the interpretation and analysis of admittance‐voltage data are discussed. The effect of degenerate statistics on the capacitance–voltage (C–V) characteristics of n‐type devices biased into accumulation and p‐type devices biased into inversion is demonstrated experimentally on MIS test devices with native oxide interfaces. Theoretical calculations using degenerate statistics and the k⋅p approximation are shown to predict the observed C–V behavior. Tunneling via Shockley–Read levels as it affects thermal equilibrium measurements of admittance‐voltage data is compared for the cases of p‐type and n‐type devices. Inversion layer quantization effects are observed in p‐type device tunneling phenomena, while n‐type devices exhibit tunneling behavior which is very sensitive to band‐gap states near the surface. Oscillations in conductance–voltage (G–V) data on p‐type devices are attributed to inversion layer quantization effects while the droop in low‐frequency G–V data on anodic oxide interface devices on n‐type material is attributed to a high density of subsurface band‐gap states introduced during the anodic oxide growth process. Multiple flatband effects in anodic oxide MIS devices with opaque and transparent gate regions can be induced by visible light exposure which creates a lateral nonuniformity in fixed charge at the oxide–HgCdTe interface.
No takes yet. Share an insight, caveat, or question.
Beck et al. (1982) studied this question.