Pseudo Random Number Generators are widely used in VLSI Design as Test Pattern Generators for testing of digital circuits in a BIST system. The test pattern sequence generated also finds applications in cryptography. It is thus essential to design an efficient test pattern generator which utilizes least hardware, dissipates lowest power and generates most random sequence. This paper attempts to compare a few recent proposals where Linear Feedback Shift Register (LFSR) has been suitably modified to obtain an efficient architecture of a test pattern generator.
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Mittal et al. (2020) studied this question.