The fully depleted p-GaN gate concept for V th instability suppression and better gate reliability in E-HEMT GaN technology

Schottky p-GaN gates in high electron mobility transistors seem to be the preferred choice as the most suited normally-off GaN device concept thanks to their excellent performance and simple driving schemes. However, Schottky p-GaN devices also exhibit inherent threshold voltage (V th) instabilities and reliability weaknesses. In this paper, we will present the main advantages of the fully depleted (FD) device concept and will describe in detail the main advantages of the proposed approach over state-of-the-art concepts. In particular, we will describe the main working principle of this new device and present experimental evidence of its superior performance in terms of dynamic threshold voltage stability and gate reliability. Firstly, we review the FD design methodology and the underlying physics with the support of TCAD simulations. Secondly, characterization including Gate stress and lifetime assessment is deployed to prove the superiority of the proposed Gate concept in terms of V th stability and Gate reliability.