Chemical mechanical planarization (CMP) models which are able to make predictions for a full chip are highly desirable in semiconductor manufacturing. Previous models proposed to this end have largely focused on effects of pattern density. We here extend one of the proposals to include also effects of pattern-size based on a consideration of the roughness of the polishing pad. Experimental data from CMP test structures containing variations of both pattern-density and pattern-size are used to validate the model. The results are applied to both interlayer dielectric-CMP and shallow trench isolation-CMP as particularly important processes in industry.
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Vasilev et al. (2011) studied this question.
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