High quality power delivery for high performance integrated circuits is a significant design challenge. To provide high quality power, the on-chip power needs to be regulated with ultrasmall locally distributed power efficient converters. While the quality of the power supply can be efficiently addressed with distributed on-chip power supplies, the stability of these parallel connected voltage regulators is a primary concern. A passivity-based stability criterion is proposed for maintaining a stable power delivery system composed of multiple regulators. To evaluate the proposed approach, a fully integrated power delivery system with distributed on-chip low-dropout (LDO) regulators has been fabricated in a 28 nm CMOS process. The experimental results of a distributed power delivery system composed of six on-chip LDO regulators satisfy this stability criterion, yielding a stable system response within -25°C to 125°C, 10% voltage variations, and 50% to 200% load sharing variations. The system is believed to be one of the first successful silicon demonstrations of stable parallel analog LDO regulators.
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Partin-Vaisband et al. (2015) studied this question.
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