Positive Bias Stress Instability of InGaZnO TFTs With Self-Aligned Top-Gate Structure in the Threshold-Voltage Compensated Pixel

The instability induced under positive gate-bias stress (PBS) in amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) with self-aligned top-gate coplanar structure is investigated under thethreshold-voltage(VT)compensated pixel schemein the backplane of organic light-emitting diode displays and compared with that under aconstant-PBS scheme. Based on the investigation, which combines the extraction of density of states, the decomposition ofVTshift (Δ VT), and technology computer-aided design, the unreleased electric field across the gate insulator (GI) and the maintained electron concentration are observed under theVT-compensated PBS condition. Indeed, the main difference between the two schemes originates from increasingly activated electron trapping within the GI deep-level traps and from the excessive oxygen-related peroxide bond-breaking in the a-IGZO-active film, i.e., O22−+2 e⁻ →O2−+ O2−. Although the latter is quantitatively much smaller than the former, the two mechanisms are closely related to each other and should be jointly optimized. This is because a large amount of oxygen interstitials can generate a high density of GI electron traps. Since the GI deep-level trapping results in noticeableΔ VTwith an increase in PBS time, our results suggest that theΔ VTshould be seriously underestimated with respect to either the estimation of pixel lifetime or the assessment ofVT-compensated pixel-circuit schemes, if the reliability/acceleration test relies only on the constant-PBS-based single-TFT device test.