Gate-induced-drain-leakage (GIDL) in LDD p-MOSFETs has been studied. The emphasis of this paper is on the comparison of GIDL in p/sup +/-poly PMOS versus n/sup +/-poly PMOS devices. Measurements show that the GIDL is less severe in p/sup +/-poly devices. Clarification for modeling GIDL in devices with different drain structures is also provided.
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Lindert et al. (1996) studied this question.
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