This work presents a power- and area-efficient three-stage amplifier that is able to drive a large capacitive load. Removing the inner Miller capacitor and employing cascode Miller compensation in the outer compensation loop could extend the complex-pole frequency of a three-stage amplifier, but result in a high Q-factor. A local impedance attenuation block consisting of a series RC network is proposed to control the complex poles. This block attenuates the high-frequency resistance at the second-stage output and achieves an optimized tradeoff between the frequency and the Q-factor of the complex poles. As the low-frequency resistance remains unchanged, a high dc gain is maintained. Implemented in 0.13 μm CMOS process, the proposed design occupies an area of 0.0032 mm2and consumes a quiescent current of 10.5 μA. When driving a 560 pF capacitive load, it achieves a unity-gain frequency of 3.49 MHz, an average slew rate of 0.86 V/ μs, and an average settling time of 0.9 μs.
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Tan et al. (2014) studied this question.