Ultra high density three dimensional capacitors based on Si nanowires array grown on a metal layer

We report the fabrication and the characterization of chemical vapor deposition (CVD) grown silicon nanowires capacitors using a complementary-metal-oxide-semiconductor (CMOS) circuit interconnect level compatible process. Silicon nanowires have been grown by CVD on metallic interconnect lines used in today’s CMOS circuits at low temperature (<425 °C) and using copper as catalyst. The nanowire assembly develops a huge surface leading to very high measured capacitance densities reaching 18 μF/cm2, and featuring a ×23 gain when compared to the same structure without nanowires. This opens the path toward embedded capacitances technologies by using bottom-up nanowires.