A spiking neural network-in-logic architecture based on reconfigurable molybdenum disulfide dual-gate transistors with ferroelectric gating

Efficient processing of high-dimensional perceptual data is a challenge in modern electronics, as neuromorphic systems typically process all input features indiscriminately, leading to excessive neuronal activation and high energy consumption. A key issue is the lack of a hardware mechanism to suppress task-irrelevant information at the front-end before neuromorphic computation and preserve reconfigurability. Here we report a spiking neural network-in-logic computing platform in which the front-end logic and spiking neural networks are co-designed to perform task-directed input selection at the hardware level before spike generation, thereby reducing unnecessary neuronal activation. To implement this, we develop reconfigurable field-effect transistors based on dual-gate molybdenum disulfide devices incorporating a ferroelectric hafnium zirconium oxide layer. These transistors support logic, synaptic and neuronal primitives within a unified device platform. The reconfigurable transistors, which are fabricated using back-end-of-line-compatible processes, are organized into reconfigurable tiles whose roles can be reassigned across tasks, allowing logic-driven input selection to reshape the effective scale of downstream spiking neural networks. The computing architecture is validated using the Modified National Institute of Standards and Technology and Street View House Numbers benchmarks, and its system-level energy scaling with task-dependent input complexity is evaluated using real-world multitask inference. Reconfigurable dual-gate ferroelectric transistors that exhibit logic, neuronal and synapse functionalities can provide logic-based spatial pruning of inputs for a spiking neural network, reducing unnecessary neuronal activation and improving energy efficiency.