Evaluation of Residual Stress in Semiconductor Chips during Resin-Molding Process Using Piezoresistive Test Chips and a Finite Element Analysis Method

The high residual stress generated on the surface of a semiconductor chip during the assembly of a resin-molded electronic package affects the electrical characteristics of the circuit, and it sometimes causes the malfunction of the circuit. Therefore, it is necessary to evaluate the residual stress in semiconductor chips in order to ensure the reliability of the electronic package. The purpose of this study is to propose a simple method of evaluating residual stress in resin-molded semiconductor chips. In this study, the residual stress in a resin-molded semiconductor chip was measured using test chips with piezoresistive gauges. Then, linear thermoelastic finite element analysis based on the stress-free temperature was performed. This stress-free temperature was determined from the temperature dependence of the residual stress experimentally measured using the test chips. The residual stress measured using the test chips corresponds well with the results of the finite element analysis. Therefore, the present evaluation method using the combination of experimental and numerical methods is considered to be reliable and reasonable.