An Ultra-Low-Power Flip-Flop With Near-Threshold Robust Operation and Redundant-Free Internal Clock Transitions

Optimizing the power consumption of flip-flops (FFs), as basic building blocks of sequential digital circuits, can substantially reduce the power of the whole system. This work proposes a new Robust Redundant-Free Flip-Flop (RRFF) for ultra-low-power purposes that addresses both aspects that have the potential to reduce power consumption: it has static and contention-free characteristics that provide the robustness required for supply voltage scalability down to the near-threshold region and, at the same time, it eliminates all internal redundant transitions, so that the circuit exclusively consumes dynamic energy when data changes. Measurement results from a test chip fabricated in a 65-nm CMOS technology show that the RRFF achieves 63.4% clock power reduction across a wide voltage range (0.4-1.1 V) and 15.0% power reduction at 100% activity for the same supply voltage range with minimal area overhead compared to the conventional transmission gate flip-flop (TGFF).