Recent Advances in High Performance CMOS Transistors: From Planar to Non-Planar

The first decade of the 21st century has witnessed tremendous innovation in transistor architecture in the introduction of strained silicon channel, high-k/metal gate stack and non–planar 3D transistor architecture. This marked the end of the era of the traditional planar transistor scaling. The article reviews some of the recent innovations in CMOS transistors that have allowed us to maintain the pace outlined by the Moore's Law by delivering higher transistor performance with increasing energy efficiency. Technical innovations such as multiple gate transistors, high-k/metal gate transistors, ballistic channel transistors, and tunnel transistors are discussed. The natural scaling process will eventually lead to the realm of reduced dimension materials and quantum engineered devices where both difficult technical challenges and golden opportunities co-exist. To overcome the challenges, research on new nanodevice structures, different device usage models, novel electronic materials and their integration on silicon, are required.