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Fractional delay filters (FDFs) have a key role in communication systems. FDFs produce a delay that is a fraction of the sampling period. In this letter, we introduce a framework based on the B-spline interpolation and decimation procedure for design of the FDFs. The method generates precise fractional delays and is easy to implement in microprocessor and VLSI environments
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Olkkonen et al. (2007) studied this question.
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