Simulation and characterisation of sensors with intrinsic gain in LFoundry 150 nm process

Future high-luminosity particle detectors require silicon sensors with high granularity, radiation tolerance, low power consumption, and excellent timing performance. The CACTUS-GL prototype investigates the integration of an LGAD-like gain layer within the LFoundry 150 nm HV-CMOS process to improve the signal-to-noise ratio of future monolithic timing sensors. The chip contains six test structures designed to study gain layer behaviour, interpixel isolation, guard ring configurations, and breakdown limitations. First current-voltage measurements were performed on high-resistivity wafers with two gain layer doping concentrations. The results show that breakdown voltage is strongly influenced by the gain layer dose and local diode geometry. A reduced p-type gain layer concentration increases the breakdown voltage, while a structure with a higher-concentration n-well diode exhibits premature breakdown at approximately 50 V. Interpixel current measurements indicate a conductive channel at low bias, which is suppressed once the buried n layer becomes fully depleted. TCAD simulations using Synopsys Sentaurus identify local electric-field enhancement near dummy diodes and gain layer termination as the dominant breakdown mechanism, and show that extending the buried n layer by approximately 100 µm to 150 µm can improve the operating margin. These measurements and simulations demonstrate the feasibility of CACTUS-GL as a test platform for monolithic gain layer sensor development and provide design guidance for future prototypes with improved breakdown behaviour and integrated readout electronics.