Simulation Study of the Selectively Implanted Deep-N-Well for PMOS SET Mitigation

In this paper, a novel well structure for PMOS single-event transient (SET) mitigation is studied by way of technology computer-aided design (TCAD) numerical simulations. Based on a 90-nm CMOS technology, the simulation results show that the proposed selectively implanted deep-N-well (SIDNW) can significantly reduce the SET pulsewidth without area, power, and performance overheads, when compared with the conventional dual-well process. A comparison is also made with the triple-well process.