Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops

This paper describes two techniques for designing phase-frequency detectors (PFDs) with higher operating frequencies [periods of less than 8/spl times/ the delay of a fan-out-4 inverter (FO-4)] and faster frequency acquisition. Prototypes designed in 0.25-/spl mu/m CMOS process exhibit operating frequencies of 1.25 GHz [=1/(8/spl middot/FO-4)] and 1.5 GHz [=1/(6.7/spl middot/FO-4)] for two techniques, respectively, whereas a conventional PFD operates at <1 GHz [=1/(10/spl middot/FO-4)]. The two proposed PFDs achieve a capture range of 1.7/spl times/ and 1.4/spl times/ the conventional design, respectively.