A 500 mA Output-Capacitorless NMOS LDO With Dynamic Load Range Adaptation Achieving Fast Settling Time and Enhanced PSR for Chiplet Power Managements

This paper presents an output-capacitorless NMOS low-dropout regulator (LDO) capable of supporting heavy load currents up to 500 mA, while enhancing power-supply rejection (PSR) and achieving a fast load transient response. The proposed NMOS LDO incorporates a dynamic load range adaptation (DLRA) technique that adaptively adjusts the number of NMOS pass gate segments based on the load current, ensuring stable regulation with high loop gain and bandwidth across the full load current range. This approach results in a reduction of settling time by up to 87%. Furthermore, the LDO integrates a regulated voltage buffer, which includes a charge pump and an auxiliary LDO (AUX-LDO), enabling the NMOS pass gates to operate at a low dropout voltage of 100 mV without requiring an external high-voltage source. The AUX-LDO also minimizes the switching ripple from the charge pump output. Fabricated in a 40 nm CMOS process, the proposed LDO supports input voltages ranging from 0.8 to 1.0 V, with a dropout voltage of 100 mV. Measurement results show a voltage droop of 96 mV and a settling time of 52 ns in response to a current step of 300 mA with an edge time of 10 ns. Additionally, the prototype demonstrates PSR exceeding -30 dB at a ripple frequency of 1 MHz even for load currents up to 300 mA.