Design and Implementation of Gain-Offset Correction Algorithm Hardware Architecture for Grayscale and Color Images Contrast Enhancement

This paper describes the design and implementation of a novel, high-speed hardware (HW) architecture for the gain-offset correction (GOC) image contrast enhancement algorithm on an FPGA fabric. The design is extremely fast and has been shown to process megapixel image frames at frame rates greatly exceeding real-time requirements. The design is small and compact enough to fit on small FPGAs to form a low-cost image processing solution. The automated nature of the contrast enhancement operation is due to the computation of global image statistics for each image. The architecture does not store any image frames to perform this task, heavily reducing memory requirements.