Ge pMOSFETs with gate lengths down to 70 nm are fabricated in a Si-like process flow. Reducing the LDD junction depth from 24 to 21 nm effectively reduces short-channel effects. In addition, a reduced source/drain series resistance is obtained using pure boron LDD implants over BF2, resulting in a significantIONboost. Benchmarking shows the potential of Ge to outperform (strained) Si, well into the sub-100-nm regime. The 70-nm devices outperform the ITRS requirements forIONby 50%, maintaining similarIOFF, as measured at the source.
No takes yet. Share an insight, caveat, or question.
Hellings et al. (2008) studied this question.
Synapse has enriched 5 related papers. Consider them for comparative context: