Alpha-particle SEU performance of SRAM with triple well

A triple-well scheme has been implemented on an 18-Mb fast synchronous SRAM by using a high energy implant to evaluate its impact on the alpha-particle-induced accelerated soft error rate (ASER). The device uses a single poly 0.15-/spl mu/m CMOS process. The SER FIT rates have been measured from silicon with and without the triple well. In contrast to the historical literature, the measured FIT rate of the triple-well silicon shows a significant degradation of the SER FIT rate. Detailed analysis of bitmap for the flipped cell was employed to identify the degradation mechanism. It is found that the increase of the p-well resistivity and the effective contact to the p-well is the main reason of the degradation. However, in the region of solid tap to both n-well and p-well, the FIT rate is close but slightly higher than the control wafers. In addition, a trade-off between the NMOS and PMOS region is identified using two-dimensional numerical analysis. The results prove that an optimization of the well connections are needed for the triple-well scheme and the SER improvement relies on the optimization of the tradeoff effect. For high energy particles, which can penetrate much deeper into the silicon substrate, the triple well is expected to be helpful to limit the charge collection.