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An analytical expression is derived for determining the maximum solder joint shearing displacement occurring in an a real-array interconnect under global CTE mismatch loading. The result may be viewed as a “load correction factor” to be applied to the commonly used estimate which is based on the free thermal expansion of component and substrate. The new expression for the correction factor includes the following parameters: (a) dimensions and material properties of component and substrate; (b) array size and population; (c) material properties of solder; and (d) geometric parameters of the individual joints. The theoretical result is based on modeling the assembly as two circular elastic disks connected by a shear-type “elastic foundation” whose distributed shear stiffness is related to the joint/array characteristics. The analytical expression and the graphical aids presented herein may provide convenient alternatives to performing time-consuming and expensive finite element “macro-analyses” on the assembly for the purpose of specifying boundary conditions for a subsequent “micro-analysis” on a single joint.
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Heinrich et al. (1997) studied this question.
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