This paper proposes a methodology for efficient process planning of concurrent machines in electronics assembly. The particular machine type under consideration is the High Speed Chip Shooter (HSCS) for surface mount assembly. Currently, most surface mount assembly operations are modeled in a cyclic manner. The model that is proposed herein is an asynchronous (acyclic) model that augments the benefits of the unique features of this assembly machine. A heuristic algorithm is developed, referred to as the Acyclic Assembly Time (AAT) algorithm, which is based on the asynchronous model. The algorithm is thoroughly tested with orthogonal arrays, compared against previously published problems, and applied to a real life example. The AAT algorithm produced excellent results throughout the test process. By increasing the utilization of the individual mechanisms, the efficiency of the overall system naturally improves and the ultimate goal of reducing the total assembly time is achieved.
No takes yet. Share an insight, caveat, or question.
MOYER et al. (1996) studied this question.
Synapse has enriched 5 related papers. Consider them for comparative context: