Tungsten/In–Sn–O stacked source/drain electrode structure of In–Ga–Zn–O thin-film transistor for low-contact resistance and suppressing channel shortening effect

The reduction of source/drain (S/D) contact resistance by suppressing effective channel length ( L eff ) shortening after the high-temperature process is key to realizing integration of high-performance short-channel In–Ga–Zn–O (IGZO) thin-film transistors to 3D large-scale integration. In order to achieve this requirement, we propose a stacked S/D electrode structure of a metal thin film and In–Sn–O (ITO). By inserting around 2 nm tungsten thin film at the interface between the IGZO channel and ITO electrode, about 11 times improvement of on-current (drain current @ V g = 20 V, V d = 0.05 V, L g / W = 0.8/2.4 μ m) was achieved. Moreover, L eff shortening was also suppressed to less than 80 nm even after 360 °C annealing.