Fault-free digital circuits may malfunction when asynchronous inputs have critical timing combinations that result in metastable operation. This mode of failure is often overlooked in digital system design and reliability analysis. Here, we survey developments in the study of metastable behavior and identify their relevance to digital system design and reliability, and we describe and evaluate a number of techniques for reducing the probability of metastable failure.
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Kleeman et al. (1987) studied this question.
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