Serially Biased Components for Digital-RF Receiver

Reduction of total bias current using the serial biasing technique is required for RSFQ-based digital-RF receiver realization. This will have a major impact on reducing the size, weight and power consumption of the complete cryocooled receiver system. The approach is based on partitioning a homogeneous design into several isolated islands biased in series and transmitting SFQ pulses between islands, over moats through inductively-coupled driver-receiver-pairs (DRPs). Experimental data on testing of 100 DRPs connected in series are reported and bit-error-rate estimates are given. Our goal is to serially bias two sets of homogeneous circuit blocks in the digital-RF receiver design: (1) digital decimation filter (DDF) bit slices, and (2) output drivers. The correct operation of test chips containing four bit-slices of a second-order DDF, partitioned into 2 and 4 islands, are demonstrated. Results of 8 output drivers, serially biased on 2, 4, and 8 islands, are reported. Design issues of scaling to a digital-RF receiver, containing 18-20 DDF bit slices and 16 output drivers are discussed.