The paper treats the effect of layout on the electromagnetic interference (EMI) of buck converters. An optimized layout design for dc-dc synchronous buck converter is proposed for EMI reduction. Six different layout versions are analyzed with respect to loop area, loop inductance, radiating dipole moments, and far-field radiation. Optimizations are done with respect to field-effect transistor (FET), decoupling capacitor and via placement. Passive full-wave simulations are used to estimate and verify the loop inductance and far-field emissions. Those are compared with measurements. A gigahertz transverse electromagnetic (GTEM) cell is used to quantify the dipole moments in the printed circuit board (PCB) for estimating the far field and comparing to measurement.
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Bhargava et al. (2011) studied this question.
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