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In this article, we present on-wafer thru-reflect-line (TRL)-calibrated measurements of silicon test structures fabricated using STMicroelectronics' B55 technology up to 500 GHz. The structures are fabricated in two subsequent runs, and the respective structure in each run has a different design. The improvements in the test structures layout design are presented on the terminal capacitances of “open-M1,” which is an important test structure for the deembedding of the transistor accesses. The improvements are examined using high-frequency structure simulator (HFSS) electromagnetic (EM) simulations, including the RF probe models and the neighboring structures.
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Cabbia et al. (2020) studied this question.
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