Step-consistent high-throughput shared-memory communication for FMI-based co-simulation

High-throughput data exchange is a critical requirement for FMI-based co-simulation, particularly in digital twin and cyber–physical system validation scenarios involving large shared state variables. Although shared-memory communication can significantly reduce latency by eliminating redundant memory copies, naïve implementations often violate FMI step semantics when multiple consumers concurrently access shared buffers. Such violations can lead to step mismatches, torn reads, and non-deterministic simulation behavior even when wall-clock timing constraints are satisfied. This paper proposes a simulation-time-aware shared-memory communication architecture for FMI 2.0 co-simulation. The proposed design separates bulk data transfer from simulation-step coordination by introducing a dual-path mechanism consisting of high-bandwidth shared memory for payload exchange and a lightweight step-indexed synchronization channel coordinated by the FMI master. By preserving previous-step data until all consumers acknowledge completion, the architecture guarantees deterministic step-consistent visibility across multiple consumers. Extensive experiments under both clean and stress execution conditions demonstrate that relaxed shared-memory schemes achieve lower raw latency and higher throughput but suffer from step mismatches and data integrity violations. In contrast, the proposed architecture achieves zero step mismatches and zero CRC failures across all evaluated payload sizes while maintaining competitive latency scaling and stable throughput in broadcast configurations. These results highlight the importance of integrating simulation-time semantics into communication-layer design and show that the proposed approach provides a practical and FMI-compliant solution for deterministic high-throughput co-simulation.