Bayesian-Based Hypothesis Testing for Topology Error Identification in Generalized State Estimation

This paper develops a Bayesian-based hypothesis testing procedure to be applied in conjunction with topology error processing via normalized Lagrange multipliers. As an advantage over previous methods, the proposed approach eliminates the need of repeated state estimator runs for alternative hypothesis evaluation. The identification process assumes that the set of switching devices is partitioned into suspect and true subsets. A geometric test is devised to ensure that all devices with wrong status are included in the suspect set. In addition, the results of criticality analysis performed at substation physical level prevents the occurrence of matrix singularities, which otherwise would degrade the performance of topology error identification. The IEEE 24-bus test system represented at physical level is employed to evaluate the proposed approach, considering diverse substation layouts and distinct types of topology errors.