Metallic-CN-Removal-Tolerant High-Yield Six-CN-MOSFET SRAM Cell for Carbon-Based Embedded Memory

The yield and robustness of carbon-based embedded memory can be significantly degraded by the presence of metallic carbon nanotubes (m-CNs) that create short circuits in the channel arrays of CN-MOSFETs. The malfunction caused by these short circuits can be avoided by removing the m-CNs using specialized etching techniques. During the removal of metallic nanotubes, however, residual m-CNs may be left in the channel arrays of some of the transistors. Furthermore, all of the nanotubes may be etched in some of the channel arrays, thereby causing permanent open circuits and malfunction. A statistical design methodology that considers all of these possibilities related to the formation and removal of metallic nanotubes is needed for achieving functional memory circuits with high yield despite fabrication imperfections in carbon-based electronics. An m-CN-removal-tolerant high-yield six-transistor (6T) static random access memory (SRAM) cell is proposed in this paper considering the nonidealities of CN-MOSFET fabrication. A general statistical functional yield model of memory arrays with 6T SRAM cells is developed by comprehensively considering the spatial correlations among different transistors. The yield of the m-CN-removal-tolerant memory array is increased by 131 times, and read access speed is enhanced by 16.42% as compared with the standard design that does not provide any tolerance to the removal of m-CNs in a 16-nm CN transistor technology.