Impact of Saturated Spontaneous Polarization on the Endurance Fatigue of Si FeFET With Metal/Ferroelectric/Interlayer/Si Gate Structure

We investigate the impact of saturated spontaneous polarization (Pₛ)of the ferroelectric on endurance fatigue of Si FeFET with Metal/Ferroelectric/Interlayer/Si (MFIS) gate structure. We tune thePₛin the range of 25.9–6.4 μ C/cm2by changing the gate structure, such as the insertion of a dielectric layer and annealing temperature. When thePₛdecreases from 12.1 to6.4 μ C/cm2, the memory window of the device decreases while the endurance improves. When thePₛdecreases from 12.1 to8.1 μ C/cm2, the memory window disappears. However, when thePₛis lower than8.1 μ C/cm2, the memory window reappears. SmallerPₛleads to a smaller memory window, which reduces the read noise margin of the memory and is disadvantageous to endurance. Whereas smallerPₛleads to weaker charge trapping behavior, which is advantageous to endurance. Our work shows that the endurance characteristic is determined by the competition between the above two processes.