Microwave annealing with subsequent rapid thermal annealing (MWA+RTA) is proposed for HfZrOx-based germanium (Ge) p-channel ferroelectric FET (p-FeFET) memory to concurrently improve the interfacial quality while obtaining the required polarization, leading to a memory window of 2.5 V by ±4 V operation, good read latency, robust endurance up to 107 cycles for 1 bit/cell operation and each stable state for 3 bits/cell (triple-level cell, TLC) operation up to 105 cycles for the first time. Reversing the annealing sequence (RTA+MWA) degrades the performance and attests to the importance of thermal budget control. The proposed annealing scheme makes the Ge FeFETs, even with planar structure, quite competitive compared to other Si-, SiGe- and Ge-based FeFETs in terms of low-voltage TLC capability with high reliability, enabling high-density embedded memory for future nodes.
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Peng et al. (2022) studied this question.
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