Ultralow ON-Resistance SOI LDMOS With Three Separated Gates and High- k Dielectric

A novel ultralow specific on-resistance (RON,sp) SOI lateral double-diffused MOS (LDMOS) with three separated gates (TSGs) and high-k (HK) pillars is proposed and investigated by simulation. The TSGs include the planar gate (GX), the segmented trench gate (GY) between the p+ body contact regions, and the embedded trench gate (GZ) connected with HK pillars and p-well regions. First, in the on-state, the TSGs form three channels, including one lateral channel and two vertical channels, which can decrease RON,spsignificantly. Second, GYand GZare extended to the buried oxide, widening the vertical conduction area and enhancing the current density in the bulk to further reduce RON,sp. Furthermore, the electron accumulation layer (EAL) is formed not only beside the extended GYand GZ, but also along the sidewall of the drift region near the source side, thus reducing RON,spgreatly. Third, the HK pillars can increase the optimal drift doping concentration (Nd) to decrease RON,spowing to the assisted depletion effect. The device obtains an ultralow RON,spof 0.34 mΩ · cm2at BV = 97 V. Compared with the conventional LDMOS and other previous devices, the TSG-HK LDMOS achieves better tradeoff between the breakdown voltage and RON,sp.