MOESI-D: A Persistent Sole-Writer Cache-Coherence State for Commutative No-Return Atomics

Abstract—Parallel workloads in machine learning like sparse embedding updates and gradient aggregation, graph analytics, and streaming telemetry rely heavily on atomic read–modify–writes to shared counters. Although each update modifies only a few bytes, conventional cache-coherence protocols repeatedly bounce entire cache lines between processor cores, stalling execution pipelines and saturating on-chip interconnects.We introduce MOESI-D, an architectural extension that adds a persistent Delegated (D) state to the MOESI protocol, moving the update to the data rather than migrating the line to each core. Targeting commutative, no-return integer reductions (e.g., addition, min/max, bitwise masks), MOESI-D designates a single cache controller as the sole writer for a contended line. Remote updates are forwarded as compact messages and applied in place via a lightweight controller-side ALU. Because issuing cores do not require a return value, operations complete fire-and-forget, allowing out-of-order pipelines to proceed immediately while store buffers preserve memory consistency. We implemented MOESI-D in gem5 and evaluated it against conventional atomics, software flat combining, and privatization techniques across synthetic microbenchmarks, sparse kernels, and telemetry workloads. MOESI-D eliminates 99.9% of cacheline migrations under heavy contention. On out-of-order cores, fire-and forget execution yields an approximate 2× speedup over standard atomics, scaling to 5.3× when the hot working set exceeds L2 cache capacity. Detailed network simulations further demonstrate an approximate 2.1× reduction in on-chip traffic, demonstrating that hardware delegation drastically lowers communication and execution costs for shared accumulation.