Gallium oxide and gadolinium gallium oxide insulators on Si δ-doped GaAs/AlGaAs heterostructures

Test devices have been fabricated on two specially grown GaAs/AlGaAs wafers with 10 nm thick gate dielectrics composed of either Ga2O3 or a stack of Ga2O3 and Gd0.25Ga0.15O0.6. The wafers have two GaAs transport channels either side of an AlGaAs barrier containing a Si δ-doping layer. Temperature dependent capacitance-voltage (C-V) and current-voltage (I-V) studies have been performed at temperatures between 10 and 300 K. Bias cooling experiments reveal the presence of DX centers in both wafers. Both wafers show a forward bias gate leakage that is by a single activated channel at higher temperatures and by tunneling at lower temperatures. When Gd0.25Ga0.15O0.6 is included in a stack with 1 nm of Ga2O3 at the interface, the gate leakage is greatly reduced due to the larger band gap of the Gd0.25Ga0.15O0.6 layer. The different band gaps of the two oxides result in a difference in the gate voltage at the onset of leakage of ∼3 V. However, the inclusion of Gd0.25Ga0.15O0.6 in the gate insulator introduces many oxide states (≥4.70×1012 cm−2). Transmission electron microscope images of the interface region show that the growth of a Gd0.25Ga0.15O0.6 layer on Ga2O3 disturbs the well ordered Ga2O3/GaAs interface. We therefore conclude that while including Gd0.25Ga0.15O0.6 in a dielectric stack with Ga2O3 is necessary for use in device applications, the inclusion of Gd decreases the quality of the Ga2O3/GaAs interface and near interface region by introducing roughness and a large number of defect states.