A Time-Interleaved ADC With a Single-Step Relative-Prime-Rotation-Based Background Timing-Skew Calibration Using MAD-Averaging

This paper presents a fully on-chip background timing-skew calibration technique based on relative-prime rotation (RPR), which enables the simultaneous extraction of timing-skew errors. The proposed approach eliminates multi-step calibration and prevents residual-skew accumulation, resulting in fast and accurate convergence. By exploiting the mean absolute difference (MAD) between the acting reference ADC and its adjacent channel, the method extends the applicable bandwidth up to the Nyquist frequency without imposing restrictions on the number of channels. An 8(+1)-channel, 10-bit, 1.1- GS/s Time-Interleaved Successive Approximation Register Analog-to-Digital Converter (TI-SAR ADC) prototype implementing the proposed architecture was fabricated in a 28-nm CMOS process, occupying an active area of 0.16 mm2. Operating from a 1-V supply, the prototype consumes 9.5 mW and achieves 49.7-dB SNDR and 61.4-dB SFDR at a 1.1-GS/s sampling rate with a near-Nyquist input. The ADC attains a competitive Walden figure-of-merit (FOMW) of 34.7 fJ/conversion-step, with the on-chip calibration consuming only 17% of the total power.