Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing

The algorithms and the implementation of a new macro/custom cell chip-planning. placement, and global muring package arc presented. The siuudatcd-annealing-based placement algorithm m.=d.S in hvo stages. I ” the fust stage. the iuteXO”“at 8r.X around theindividual cells is determined using B new dynamic intaconnect ~TCB estimator. The second stage consists of: (1) a channel definition step, using a new channel definition algorithm, (2) a global routing step. using a new global router algorithm. and (3) a placement refinement step. This strategy has produced placements which require very little placement modification during detailed routing. Total interco~nect~lcn~th savings of 8 to 49 percent were achieved in experiments on 9 industrml cxrcmts. Furthermore, circuit-area reductions ranged from 4 to 56 percent versus a variety of other placement methods. 1.