An anti-ferroelectric gated Landau transistor to achieve sub-60 mV/dec switching at low voltage and high speed

Landau field effect transistors promise to lower the power-dissipation of integrated circuits (ICs) by reducing the subthreshold swing (S) below the Boltzmann limit of 60 mV/dec. The key idea is to replace the classical gate insulator with dielectrics that exhibit negative capacitance (NC) associated with double-well energy landscape, for example, ferroelectrics (FE), air-gap capacitors, or a combination thereof. Indeed, S is dramatically reduced, constrained only by the limits of hysteresis-free operation. Unfortunately, the following limitations apply (i) the need for capacitance matching constrains steep S only to the small subthreshold region for FE based negative capacitance field effect transistor (NCFET) and requires an insulator too thick for sub-20 nm scaling; (ii) the kinetics of mechanical switching for airgap based NCFET obviate high-speed operation; and (iii) the lattice mismatch between the substrate and the dielectric makes defect-free integration difficult. In this article, we demonstrate that a FET integrated with 10 nm HfO2-based anti-ferroelectric and FE hetero stack would achieve ultralow S with ON-current (Ion) at par with classical transistors at significantly lower voltage and would simplify integration. Our results address the well-known challenges/criticisms of classical Landau transistors, thereby, making them technology relevant for modern ICs.